• Fast HUB Floating-point Adder for FPGA 

      Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; Gonzalez-Navarro, Sonia (2018-10-17)
      Several previous publications have shown the area and delay reduction when implementing real number computation using HUB formats for both floating-point and fixed-point. In this paper, we present a HUB floating-point ...
    • Measuring Improvement when Using HUB Formats to Implement Floating-Point Systems under Round-to-Nearest 

      Hormigo-Aguilar, Javier; Villalba-Moreno, Julio (IEEE, 2016)
      This paper analyzes the benefits of using HUB formats to implement floating-point arithmetic under round-tonearest mode from a quantitative point of view. Using HUB formats to represent numbers allows the removal of the ...
    • New formats for computing with real-numbers under round-to-nearest 

      Hormigo-Aguilar, Javier; Villalba-Moreno, Julio (2015-09-17)
      In this paper, a new family of formats to deal with real number for applications requiring round to nearest is proposed. They are based on shifting the set of exactly represented numbers which are used in conventional ...
    • Unbiased Rounding for HUB Floating-point Addition 

      Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; Gonzalez-Navarro, Sonia (2018-06-28)
      Half-Unit-Biased (HUB) is an emerging format based on shifting the represented numbers by half Unit in the Last Place. This format simplifies two’s complement and roundto- nearest operations by preventing any carry ...