• Fast HUB Floating-point Adder for FPGA 

      Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; Gonzalez-Navarro, Sonia (2018-10-17)
      Several previous publications have shown the area and delay reduction when implementing real number computation using HUB formats for both floating-point and fixed-point. In this paper, we present a HUB floating-point ...
    • New Results on Non-normalized Floating-point Formats 

      Gonzalez-Navarro, Sonia; Hormigo-Aguilar, Javier (IEEE Computer Society, 2019)
      Compulsory normalization of the represented numbers is a key requirement of the floating-point standard. This requirement contributes to fundamental characteristics of the standard, such as taking the most of the precision ...
    • Unbiased Rounding for HUB Floating-point Addition 

      Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; Gonzalez-Navarro, Sonia (2018-06-28)
      Half-Unit-Biased (HUB) is an emerging format based on shifting the represented numbers by half Unit in the Last Place. This format simplifies two’s complement and roundto- nearest operations by preventing any carry ...