Listar AC - Artículos por autor "Hormigo-Aguilar, Javier"
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Designing a Project for Learning Industry 4.0 by Applying IoT to Urban Garden
Hormigo-Aguilar, Javier; Rodríguez-Moreno, Andrés (2019-10-11)The fast evolution of technologies forces teachers to trade content off for self-learning. Project-based learning (PBL) is one of the best ways to promote self-learning and simultaneously boost motivation. In this paper, ... -
Efficient floating-point givens rotation unit
Hormigo-Aguilar, Javier; Muñoz, Sergio (2020-10-23)High-throughput QR decomposition is a key operation in many advanced signal processing and communication applications. For some of these applications, using floating-point computation is becoming almost compulsory. However, ... -
Fast HUB Floating-point Adder for FPGA
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; González-Navarro, Sonia (2018-10-17)Several previous publications have shown the area and delay reduction when implementing real number computation using HUB formats for both floating-point and fixed-point. In this paper, we present a HUB floating-point ... -
High-Radix Formats for Enhancing Floating-Point FPGA Implementations
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier (Springer, 2021-12-02)This article proposes a family of high-radix floating-point representation to efficiently deal with floating-point addition in FPGA devices with no native floating-point sup port. Since variable shifter implementation ... -
High-radix formats for enhancing floating-point FPGA implementations
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier (Springer, 2022-03)This article proposes a family of high-radix floating-point representation to efficiently deal with floating-point addition in FPGA devices with no native floating-point support. Since variable shifter implementation ... -
High-Throughput FPGA Implementation of QR Decomposition
Muñoz, Sergio D.; Hormigo-Aguilar, Javier (2015-09-17)This brief presents a hardware design to achieve high-throughput QR decomposition, using Givens Rotation Method. It utilizes a new two-dimensional systolic array architecture with pipelined processing elements, which are ... -
HUB meets posit: arithmetic units implementation
Murillo, Raul; Hormigo-Aguilar, Javier; del Barrio, Alberto A.; Botella, Guillermo (IEEE, 2023)The posit (TM) format was introduced in 2017 as an alternative to replacing the widespread IEEE 754. Posit arithmetic provides reproducible results across platforms and possesses tapered accuracy, among other improvemen ... -
Measuring Improvement when Using HUB Formats to Implement Floating-Point Systems under Round-to-Nearest
Hormigo-Aguilar, Javier; Villalba-Moreno, Julio (IEEE, 2016)This paper analyzes the benefits of using HUB formats to implement floating-point arithmetic under round-tonearest mode from a quantitative point of view. Using HUB formats to represent numbers allows the removal of the ... -
New formats for computing with real-numbers under round-to-nearest
Hormigo-Aguilar, Javier; Villalba-Moreno, Julio (2015-09-17)In this paper, a new family of formats to deal with real number for applications requiring round to nearest is proposed. They are based on shifting the set of exactly represented numbers which are used in conventional ... -
New Results on Non-normalized Floating-point Formats
González-Navarro, Sonia; Hormigo-Aguilar, Javier (IEEE Computer Society, 2019)Compulsory normalization of the represented numbers is a key requirement of the floating-point standard. This requirement contributes to fundamental characteristics of the standard, such as taking the most of the precision ... -
Unbiased Rounding for HUB Floating-point Addition
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; González-Navarro, Sonia (2018-06-28)Half-Unit-Biased (HUB) is an emerging format based on shifting the represented numbers by half Unit in the Last Place. This format simplifies two’s complement and roundto- nearest operations by preventing any carry ...