Listar AC - Artículos por título
Mostrando ítems 9-28 de 64
-
A Comparative Analysis of STM Approaches to Reduction Operations in Irregular Applications
Pedrero-Luque, Manuel
; Gutiérrez-Carrasco, Eladio Damián; Romero-Montiel, Sergio; Plata-González, Óscar Guillermo
As a recently consolidated paradigm for optimistic concurrency in modern multicore architectures, Transactional Memory (TM) can help to the exploitation of parallelism in irregular applications when data dependence ... -
Comparing assembly strategies for third-generation sequencing technologies across different genomes
Espinosa García, Elena María; Bautista-Moreno, Rocío; Fernández, Iván; Larrosa-Jiménez, Rafael; López-Zapata, Emilio; Plata-González, Óscar Guillermo[et al.] (Elsevier, 2023-09)
The recent advent of long-read sequencing technologies, such as Pacific Biosciences (PacBio) and Oxford Nanopore technology (ONT), has led to substantial accuracy and computational cost improvements. However, de novo ... -
CPU and GPU oriented optimizations for LiDAR data processing
Muñoz, Felipe; Asenjo-Plaza, Rafael; Navarro, Ángeles; Cabaleiro, J. Carlos (Elsevier, 2024-07)
Digital Terrain Models (DTM) can be accurately obtained from clouds of LiDAR points but the corresponding cloud processing time can be prohibitive. This paper describes several optimization techniques that have been applied ... -
Design optimization of a 3-stage membrane cascade for oligosaccharides purification using mixed integer non-linear programming.
Rizki, Zulhaj; Janssen, Anja E.M.; Hendrix, Eligius María Theodorus; van der Padt, Albert; Boom, Remko M.; Claassen, G.D.H.[et al.] (2020)
Inhomogeneous membrane cascade systems have been utilized to purify fructooligosaccharides (FOS). Such a process allows a different setup at every stage of the cascade. Varying the setup at every stage implies an optimization ... -
Designing a Project for Learning Industry 4.0 by Applying IoT to Urban Garden
Hormigo-Aguilar, Javier; Rodríguez-Moreno, Andrés (2019-10-11)
The fast evolution of technologies forces teachers to trade content off for self-learning. Project-based learning (PBL) is one of the best ways to promote self-learning and simultaneously boost motivation. In this paper, ... -
Efficient floating-point givens rotation unit
Hormigo-Aguilar, Javier; Muñoz, Sergio (2020-10-23)
High-throughput QR decomposition is a key operation in many advanced signal processing and communication applications. For some of these applications, using floating-point computation is becoming almost compulsory. However, ... -
Efficient heterogeneous matrix profile on a CPU + High Performance FPGA with integrated HBM
Romero Moreno, José Carlos; González-Navarro, María Ángeles; Vilches Reina, Antonio; Corbera-Peña, Francisco Javier (Elsevier, 2021-12)
In this work, we study the problem of efficiently executing a state-of-the-art time series algorithm class – SCAMP – on a heterogeneous platform comprised of CPU + High Performance FPGA with integrated HBM (High Bandwidth ... -
Enabling Fast and Energy-Efficient FM-index Exact Matching using Processing-Near-Memory
Herruzo-Ruiz, José Manuel; Fernández, Iván; González-Navarro, Sonia; Óscar, Plata (Springer, 2021-09)
Memory bandwidth and latency constitutes a major performance bottleneck for many data-intensive applications. While high-locality access patterns take advantage of the deep cache hierarchies available in modern processors, ... -
Energy-based tuning of convolution neural networks on multi-GPUs
Castro Payán, Francisco Manuel; Guil-Mata, Nicolás; Marín Jiménez, Manuel Jesús; Pérez-Serrano, Jesús; Ujaldon-Martínez, Manuel (Wiley, 2019-11)
Deep Learning (DL) applications are gaining momentum in the realm of Artificial Intelligence, particularly after GPUs have demonstrated remarkable skills for accelerating their challenging computational requirements. Within ... -
Energy-based tuning of metaheuristics for molecular docking on multi-GPUs
Pérez-Serrano, Jesús; Imbernón, Baldomero; Cecilia, José María; Ujaldon-Martínez, Manuel (Wiley, 2018-09)
Virtual Screening (VS) methods simulate molecular interactions in silico to look for the best chemical compound that interacts with a given molecular target. VS is becoming increasingly popular to accelerate the drug ... -
Enhancing Scalability In Best-Effort Hardware Transactional Memory Systems
Quislant-del-Barrio, Ricardo; Gutiérrez-Carrasco, Eladio Damián; López-Zapata, Emilio; Plata-González, Óscar Guillermo (Elsevier, 2017)
Current industry proposals for hardware transactional memory focus on best-effort solutions where hardware limits are imposed on transactions. These designs can efficiently execute transactions but they may abort due to ... -
Experiments with Active-Set LP Algorithms Allowing Basis Deficiency
Hendrix, Eligius María Theodorus; Guerrero-García, Pablo (IOAP-MDPI, 2022-12-23)
n interesting question for linear programming (LP) algorithms is how to deal with solutions in which the number of nonzero variables is less than the number of rows of the matrix in standard form. An approach is that of ... -
Exploring multiprocessor approaches to time series analysis
Quislant-del-Barrio, Ricardo; Gutiérrez-Carrasco, Eladio Damián; Plata-González, Óscar Guillermo (Elsevier, 2024-02-08)
A time series is a chronologically ordered set of samples of a real-valued variable that can have millions of observations. Time series analysis seeks extracting models in a large variety of domains [31] such as epidemiology, ... -
Fast HUB Floating-point Adder for FPGA
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; González-Navarro, Sonia (2018-10-17)
Several previous publications have shown the area and delay reduction when implementing real number computation using HUB formats for both floating-point and fixed-point. In this paper, we present a HUB floating-point ... -
Fisher Motion Descriptor for Multiview Gait Recognition.
Castro, Francisco M.; Marín Jiménez, Manuel Jesús; Guil-Mata, Nicolás; Muñoz-Salinas, Rafael (World Scientific, 2017)
This paper aims to identify individuals by analyzing their gait using motion descriptors based on densely sampled short-term trajectories, instead of traditional binary silhouettes. The approach leverages advanced people ... -
Floating Point HUB Adder for RISC-V Sargantana Processor
Bandera-Burgueño, Gerardo; Salamero, Javier; Moreto, Miquel; Villalba-Moreno, Julio (Cornell University, 2023)
HUB format is an emerging technique to improve the hardware and time requirement when round to nearest is needed. On the other hand, RISC-V is a open source ISA that an important number of companies are using in their ... -
Genome Sequence Alignment - Design Space Exploration for Optimal Performance and Energy Architectures
Qureshi, Yasir Mahmood; Herruzo-Ruiz, José Manuel; Zapater, Marina; Olcoz, Katzalin; González-Navarro, Sonia; Óscar, Plata; Atienza, David[et al.] (IEEE Transactions on Computers, 2021-12)
Next generation workloads, such as genome sequencing, have an astounding impact in the healthcare sector. Sequence alignment, the first step in genome sequencing, has experienced recent breakthroughs, which resulted in ... -
Hardware Signature Designs to Deal With Asymmetry in Transactional Data Sets
Quislant-del-Barrio, Ricardo; Gutiérrez-Carrasco, Eladio Damián; Plata-González, Óscar Guillermo; López-Zapata, Emilio (IEEE, 2013)
Transactional Memory (TM) systems must track memory accesses made by concurrent transactions in order to detect conflicts. Many TM implementations use signatures for this purpose, which summarize reads and writes in ... -
High-Radix Formats for Enhancing Floating-Point FPGA Implementations
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier (Springer, 2021-12-02)
This article proposes a family of high-radix floating-point representation to efficiently deal with floating-point addition in FPGA devices with no native floating-point sup port. Since variable shifter implementation ... -
High-radix formats for enhancing floating-point FPGA implementations
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier (Springer, 2022-03)
This article proposes a family of high-radix floating-point representation to efficiently deal with floating-point addition in FPGA devices with no native floating-point support. Since variable shifter implementation ...