Listar AC - Artículos por título
Mostrando ítems 3-18 de 18
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Efficient floating-point givens rotation unit
Hormigo-Aguilar, Javier
; Muñoz, Sergio (2020-10-23)
High-throughput QR decomposition is a key operation in many advanced signal processing and communication applications. For some of these applications, using floating-point computation is becoming almost compulsory. However, ... -
Efficient heterogeneous matrix profile on a CPU + High Performance FPGA with integrated HBM
Romero Moreno, José Carlos; González Navarro, Mª Angeles; Vilches, Antonio; Corbera, Francisco (Elsevier, 2021-12)
In this work, we study the problem of efficiently executing a state-of-the-art time series algorithm class – SCAMP – on a heterogeneous platform comprised of CPU + High Performance FPGA with integrated HBM (High Bandwidth ... -
Experiments with Active-Set LP Algorithms Allowing Basis Deficiency
Hendrix, Eligius Maria Theodorus; Guerrero-Garcia, Pablo (IOAP-MDPI, 2022-12-23)
n interesting question for linear programming (LP) algorithms is how to deal with solutions in which the number of nonzero variables is less than the number of rows of the matrix in standard form. An approach is that of ... -
Fast HUB Floating-point Adder for FPGA
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; Gonzalez-Navarro, Sonia (2018-10-17)
Several previous publications have shown the area and delay reduction when implementing real number computation using HUB formats for both floating-point and fixed-point. In this paper, we present a HUB floating-point ... -
High-Radix Formats for Enhancing Floating-Point FPGA Implementations
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier (Springer, 2021-12-02)
This article proposes a family of high-radix floating-point representation to efficiently deal with floating-point addition in FPGA devices with no native floating-point sup port. Since variable shifter implementation ... -
High-Throughput FPGA Implementation of QR Decomposition
Muñoz, Sergio D.; Hormigo-Aguilar, Javier (2015-09-17)
This brief presents a hardware design to achieve high-throughput QR decomposition, using Givens Rotation Method. It utilizes a new two-dimensional systolic array architecture with pipelined processing elements, which are ... -
Inventory control for a non-stationary demand perishable product: comparing policies and solution methods
Hendrix, Eligius Maria Theodorus; Pauls-Worm, Karin G.J (2018-03-02)
This paper summarizes our findings with respect to order policies for an inventory control problem for a perishable product with a maximum fixed shelf life in a periodic review system, where chance constraints play a role. ... -
Lightweight asynchronous scheduling in heterogeneous reconfigurable systems
Rodriguez-Moreno, Andres; Gonzalez-Navarro, Maria Angeles; Nikov, Kris; Nunez-Yanez, José; Gran-Tejero, Rubén; Suárez Gracia, Darío; Asenjo, Rafael[et al.] (Elsevier, 2022-03)
The trend for heterogeneous embedded systems is the integration of accelerators and general-purpose CPU cores on the same die. In these integrated architectures, like the Zynq UltraScale+ board (CPU+FPGA) that we target ... -
Measuring Improvement when Using HUB Formats to Implement Floating-Point Systems under Round-to-Nearest
Hormigo-Aguilar, Javier; Villalba-Moreno, Julio (IEEE, 2016)
This paper analyzes the benefits of using HUB formats to implement floating-point arithmetic under round-tonearest mode from a quantitative point of view. Using HUB formats to represent numbers allows the removal of the ... -
Mejorando el rendimiento de la memoria transaccional para aplicaciones irregulares
Pedrero-Luque, Manuel; Gutierrez-Carrasco, Eladio Damian; Romero-Montiel, Sergio; Plata-Gonzalez, Oscar Guillermo (2018-11-15)
La Memoria Transaccional (TM) ofrece un modelo de ejecución concurrente optimista en arquitecturas multinúcleo, permitiendo a los programadores extraer paralelismo cuando la información de las dependencias de datos no está ... -
New formats for computing with real-numbers under round-to-nearest
Hormigo-Aguilar, Javier; Villalba-Moreno, Julio (2015-09-17)
In this paper, a new family of formats to deal with real number for applications requiring round to nearest is proposed. They are based on shifting the set of exactly represented numbers which are used in conventional ... -
New Results on Non-normalized Floating-point Formats
Gonzalez-Navarro, Sonia; Hormigo-Aguilar, Javier (IEEE Computer Society, 2019)
Compulsory normalization of the represented numbers is a key requirement of the floating-point standard. This requirement contributes to fundamental characteristics of the standard, such as taking the most of the precision ... -
Speculative Barriers with Transactional Memory
Pedrero-Luque, Manuel; Quislant-del-Barrio, Ricardo; Gutierrez-Carrasco, Eladio Damian; López-Zapata, Emilio; Plata-Gonzalez, Oscar Guillermo (IEEE, 2020-12-14)
Transactional Memory (TM) is a synchronization model for parallel programming which provides optimistic concurrency control. Transactions can run in parallel and are only serialized in case of conflict. In this work we use ... -
TraTSA: A Transprecision Framework for Efficient Time Series Analysis
Fernández-Vega, Iván; Quislant-del-Barrio, Ricardo; Gonzalez-Navarro, Sonia; Gutierrez-Carrasco, Eladio Damian; Plata, Óscar G. (Elsevier, 2022-09)
Time series analysis (TSA) comprises methods for extracting information in domains as diverse as medicine, seismology, speech recognition and economics. Matrix Profile (MP) is the state-of-the-art TSA technique, which ... -
Unbiased Rounding for HUB Floating-point Addition
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; Gonzalez-Navarro, Sonia (2018-06-28)
Half-Unit-Biased (HUB) is an emerging format based on shifting the represented numbers by half Unit in the Last Place. This format simplifies two’s complement and roundto- nearest operations by preventing any carry ...