Listar AC - Artículos por tipo "info:eu-repo/semantics/article"
Mostrando ítems 1-20 de 39
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A data relocation approach for terrain surface analysis on multi-GPU systems: a case study on the total viewshed problem.
(Taylor & Francis, 2020-12-04)Digital Elevation Models (DEMs) are important datasets for modelling line-of-sight phenomena such as radio signals, sound waves and human vision. These are commonly analysed using rotational sweep algorithms. However, ... -
Accelerating Sequence Alignments Based on FM-Index Using the Intel KNL Processor
(IEEE/ACM TRANSACTIONS ON COMPUTATIONAL BIOLOGY AND BIOINFORMATICS,, 2020-07-01)FM-index is a compact data structure suitable for fast matches of short reads to large reference genomes. The matching algorithm using this index exhibits irregular memory access patterns that cause frequent cache misses, ... -
Artificial intelligence to assist specialists in the detection of haematological diseases
(Elsevier, 2023)Artificial intelligence, particularly the growth of neural network research and development, has become an invaluable tool for data analysis, offering unrivalled solutions for image generation, natural language processing, ... -
A Comparative Analysis of STM Approaches to Reduction Operations in Irregular Applications
As a recently consolidated paradigm for optimistic concurrency in modern multicore architectures, Transactional Memory (TM) can help to the exploitation of parallelism in irregular applications when data dependence ... -
Comparing assembly strategies for third-generation sequencing technologies across different genomes
(Elsevier, 2023-09)The recent advent of long-read sequencing technologies, such as Pacific Biosciences (PacBio) and Oxford Nanopore technology (ONT), has led to substantial accuracy and computational cost improvements. However, de novo ... -
Designing a Project for Learning Industry 4.0 by Applying IoT to Urban Garden
(2019-10-11)The fast evolution of technologies forces teachers to trade content off for self-learning. Project-based learning (PBL) is one of the best ways to promote self-learning and simultaneously boost motivation. In this paper, ... -
Efficient floating-point givens rotation unit
(2020-10-23)High-throughput QR decomposition is a key operation in many advanced signal processing and communication applications. For some of these applications, using floating-point computation is becoming almost compulsory. However, ... -
Efficient heterogeneous matrix profile on a CPU + High Performance FPGA with integrated HBM
(Elsevier, 2021-12)In this work, we study the problem of efficiently executing a state-of-the-art time series algorithm class – SCAMP – on a heterogeneous platform comprised of CPU + High Performance FPGA with integrated HBM (High Bandwidth ... -
Enabling Fast and Energy-Efficient FM-index Exact Matching using Processing-Near-Memory
(Springer, 2021-09)Memory bandwidth and latency constitutes a major performance bottleneck for many data-intensive applications. While high-locality access patterns take advantage of the deep cache hierarchies available in modern processors, ... -
Energy-based tuning of convolution neural networks on multi-GPUs
(Wiley, 2019-11)Deep Learning (DL) applications are gaining momentum in the realm of Artificial Intelligence, particularly after GPUs have demonstrated remarkable skills for accelerating their challenging computational requirements. Within ... -
Energy-based tuning of metaheuristics for molecular docking on multi-GPUs
(Wiley, 2018-09)Virtual Screening (VS) methods simulate molecular interactions in silico to look for the best chemical compound that interacts with a given molecular target. VS is becoming increasingly popular to accelerate the drug ... -
Experiments with Active-Set LP Algorithms Allowing Basis Deficiency
(IOAP-MDPI, 2022-12-23)n interesting question for linear programming (LP) algorithms is how to deal with solutions in which the number of nonzero variables is less than the number of rows of the matrix in standard form. An approach is that of ... -
Exploring multiprocessor approaches to time series analysis
(Elsevier, 2024-02-08)A time series is a chronologically ordered set of samples of a real-valued variable that can have millions of observations. Time series analysis seeks extracting models in a large variety of domains [31] such as epidemiology, ... -
Fast HUB Floating-point Adder for FPGA
(2018-10-17)Several previous publications have shown the area and delay reduction when implementing real number computation using HUB formats for both floating-point and fixed-point. In this paper, we present a HUB floating-point ... -
Floating Point HUB Adder for RISC-V Sargantana Processor
(Cornell University, 2023)HUB format is an emerging technique to improve the hardware and time requirement when round to nearest is needed. On the other hand, RISC-V is a open source ISA that an important number of companies are using in their ... -
Genome Sequence Alignment - Design Space Exploration for Optimal Performance and Energy Architectures
(IEEE Transactions on Computers, 2021-12)Next generation workloads, such as genome sequencing, have an astounding impact in the healthcare sector. Sequence alignment, the first step in genome sequencing, has experienced recent breakthroughs, which resulted in ... -
High-Radix Formats for Enhancing Floating-Point FPGA Implementations
(Springer, 2021-12-02)This article proposes a family of high-radix floating-point representation to efficiently deal with floating-point addition in FPGA devices with no native floating-point sup port. Since variable shifter implementation ... -
High-radix formats for enhancing floating-point FPGA implementations
(Springer, 2022-03)This article proposes a family of high-radix floating-point representation to efficiently deal with floating-point addition in FPGA devices with no native floating-point support. Since variable shifter implementation ... -
High-Throughput FPGA Implementation of QR Decomposition
(2015-09-17)This brief presents a hardware design to achieve high-throughput QR decomposition, using Givens Rotation Method. It utilizes a new two-dimensional systolic array architecture with pipelined processing elements, which are ...