• A Comparative Analysis of STM Approaches to Reduction Operations in Irregular Applications 

      Pedrero, Manuel; Gutierrez-Carrasco, Eladio Damian; Romero-Montiel, Sergio; Plata-Gonzalez, Oscar Guillermo
      As a recently consolidated paradigm for optimistic concurrency in modern multicore architectures, Transactional Memory (TM) can help to the exploitation of parallelism in irregular applications when data dependence ...
    • High-Throughput FPGA Implementation of QR Decomposition 

      Muñoz, Sergio D.; Hormigo-Aguilar, Javier (2015-09-17)
      This brief presents a hardware design to achieve high-throughput QR decomposition, using Givens Rotation Method. It utilizes a new two-dimensional systolic array architecture with pipelined processing elements, which are ...
    • New formats for computing with real-numbers under round-to-nearest 

      Hormigo-Aguilar, Javier; Villalba-Moreno, Julio (2015-09-17)
      In this paper, a new family of formats to deal with real number for applications requiring round to nearest is proposed. They are based on shifting the set of exactly represented numbers which are used in conventional ...
    • New Results on Non-normalized Floating-point Formats 

      Gonzalez-Navarro, Sonia; Hormigo-Aguilar, Javier (IEEE Computer Society, 2019)
      Compulsory normalization of the represented numbers is a key requirement of the floating-point standard. This requirement contributes to fundamental characteristics of the standard, such as taking the most of the precision ...
    • Unbiased Rounding for HUB Floating-point Addition 

      Villalba, Julio; Hormigo, Javier; González-Navarro, Sonia; Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; [et al.] (2018-06-28)
      Half-Unit-Biased (HUB) is an emerging format based on shifting the represented numbers by half Unit in the Last Place. This format simplifies two’s complement and roundto- nearest operations by preventing any carry ...