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Arquitectura HW para decodificador Two-Step SOVA con recorridos hacia atrás sistólicos
| dc.contributor.author | Martín-Vega, Francisco J. | |
| dc.contributor.author | Lopez-Martinez, F. Javier | |
| dc.contributor.author | Entrambasaguas-Muñoz, José Tomás | |
| dc.date.accessioned | 2022-02-06T21:31:50Z | |
| dc.date.available | 2022-02-06T21:31:50Z | |
| dc.date.issued | 2012-09-12 | |
| dc.identifier.uri | https://hdl.handle.net/10630/23749 | |
| dc.description.abstract | In this paper, a novel SOVA (Soft-Output Viterbi algorithm) decoder using systolic arrays to carry out the trace-back method is presented. Systolic arrays are associated with high data rates and small resource requirements, so they are especially attractive for efficient hardware implementations. The proposed architecture offers excellent performance in terms of throughput and has been used to implement a turbo decoder compliant to the 3GPP-LTE specification. | es_ES |
| dc.description.sponsorship | Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech. | es_ES |
| dc.language.iso | spa | es_ES |
| dc.rights | info:eu-repo/semantics/openAccess | es_ES |
| dc.subject | Sistemas informáticos | es_ES |
| dc.subject.other | FPGA | es_ES |
| dc.subject.other | codificación de canal | es_ES |
| dc.subject.other | turbo decodificación | es_ES |
| dc.subject.other | soft-output Viterbi algorithm | es_ES |
| dc.subject.other | LTE | es_ES |
| dc.title | Arquitectura HW para decodificador Two-Step SOVA con recorridos hacia atrás sistólicos | es_ES |
| dc.type | info:eu-repo/semantics/conferenceObject | es_ES |
| dc.centro | E.T.S.I. Telecomunicación | es_ES |
| dc.relation.eventtitle | XXVII Simposium Nacional de la Unión Científica Internacional de Radio (URSI) | es_ES |
| dc.relation.eventplace | Elche (Spain) | es_ES |
| dc.relation.eventdate | 12/09/2012 | es_ES |