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dc.contributor.authorRomero Moreno, José Carlos
dc.contributor.authorGonzález-Navarro, María Ángeles 
dc.contributor.authorVilches Reina, Antonio
dc.contributor.authorCorbera-Peña, Francisco Javier 
dc.date.accessioned2022-04-28T10:09:14Z
dc.date.available2022-04-28T10:09:14Z
dc.date.issued2021-12
dc.identifier.citationRomero Moreno, José Carlos ; González Navarro, Mª Angeles ; Vilches, Antonio ; Corbera Peña, Francisco Javier. Efficient heterogeneous matrix profile on a CPU + High Performance FPGA with integrated HBM. Future Generation Computer Systems Volume 125, December 2021, Pages 10-23. https://doi.org/10.1016/j.future.2021.06.025es_ES
dc.identifier.urihttps://hdl.handle.net/10630/23998
dc.description.abstractIn this work, we study the problem of efficiently executing a state-of-the-art time series algorithm class – SCAMP – on a heterogeneous platform comprised of CPU + High Performance FPGA with integrated HBM (High Bandwidth Memory). The geometry of the algorithm (a triangular matrix walk) and the FPGA capabilities pose two challenges. First, several replicated IPs can be instantiated in the FPGA fabric, so load balance is an issue not only at system-level (CPU+FPGA), but also at device-level (FPGA IPs). And second, the data that each one of these IPs accesses must be carefully placed among the HBM banks in order to efficiently exploit the memory bandwidth offered by the banks while optimizing power consumption. To tackle the first challenge we propose a novel hierarchical scheduler named Fastfit, to efficiently balance the workload in the heterogeneous system while ensuring near-optimal throughput. Our scheduler consists of a two level scheduling engine: (1) the system-level scheduler, which leverages an analytical model of the FPGA pipeline IPs, to find the near-optimal FPGA chunk size that guarantees optimal FPGA throughput; and (2) a geometry-aware device-level scheduler, which is responsible for the effective partitioning of the FPGA chunk into sub-chunks assigned to each FPGA IP. To deal with the second challenge we propose a methodology based on a model of the HBM bandwidth usage that allows us to set the minimum number of active banks that ensure the maximum aggregated memory bandwidth for a given number of IPs. Through exhaustive evaluation we validate the accuracy of our models, the efficiency of our intra-device partition strategies and the performance and energy efficiency of our Fastfit heterogeneous scheduler, finding that it outperforms state-of-the-art previous schedulers by achieving up to 99.4% of ideal performance.es_ES
dc.description.sponsorshipThis work has been supported by the Spanish project TIN2016-80920-R, by Junta de Andalucía under research projects UMA18- FEDERJA-108. Funding for open access charge: Universidad de Málaga/CBUA.es_ES
dc.language.isoenges_ES
dc.publisherElsevieres_ES
dc.rightsinfo:eu-repo/semantics/openAccesses_ES
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/*
dc.subjectAnálisis de series temporaleses_ES
dc.subject.otherHigh Performance FPGAes_ES
dc.subject.otherHigh Bandwidth Memoryes_ES
dc.subject.otherHeterogeneous scheduleres_ES
dc.subject.otherLightweight partitioneres_ES
dc.subject.otherAnalytical modeles_ES
dc.subject.otherTime serieses_ES
dc.titleEfficient heterogeneous matrix profile on a CPU + High Performance FPGA with integrated HBMes_ES
dc.typeinfo:eu-repo/semantics/articlees_ES
dc.centroE.T.S.I. Informáticaes_ES
dc.identifier.doihttps://doi.org/10.1016/j.future.2021.06.025
dc.rights.ccAtribución 4.0 Internacional*


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