Listar AC - Contribuciones a congresos científicos por autor "Hormigo-Aguilar, Javier"
Mostrando ítems 1-8 de 8
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Efficient Floating-Point Representation for Balanced Codes for FPGA Devices
Villalba-Moreno, Julio
; Hormigo-Aguilar, Javier; Corbera, Francisco; Gonzalez, Mario; López-Zapata, Emilio (2013-10-30)
We propose a floating–point representation to deal efficiently with arithmetic operations in codes with a balanced number of additions and multiplications for FPGA devices. The variable shift operation is very slow in ... -
Floating Point Square Root under HUB Format
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier (2017-09-26)
Unit-Biased (HUB) is an emerging format based on shifting the representation line of the binary numbers by half unit in the last place. The HUB format is specially relevant for computers where rounding to nearest is ... -
Improving Fixed-Point Implementation of QR Decomposition by Rounding-to-Nearest
Muñoz, Sergio D.; Hormigo-Aguilar, Javier (2015-06-29)
QR decomposition is a key operation in many current communication systems. This paper shows how to reduce the area of a fixed-point QR decomposition implementation based on Givens rotations by using a new number ... -
Normalizing or not normalizing? An open question for floating-point arithmetic in embedded systems
Gonzalez-Navarro, Sonia; Hormigo-Aguilar, Javier (IEEE, 2017-07-24)
Emerging embedded applications lack of a specific standard when they require floating-point arithmetic. In this situation they use the IEEE-754 standard or ad hoc variations of it. However, this standard was not designed ... -
Optimizing DSP Circuits by a New Family of Arithmetic Operators
Hormigo-Aguilar, Javier; Villalba-Moreno, Julio (2014-11-19)
A new family of arithmetic operators to optimize the implementation of circuits for digital signal processing is presented. Thanks to use of a new technique which reduces the quantification errors, the proposed operators ... -
Project based learning on industrial informatics: applying IoT to urban garden
Hormigo-Aguilar, Javier; Rodriguez-Moreno, Andres (2018-06-28)
The fast evolution of technologies forces teachers to trade content off for self-learning. PBL is one of the best ways to promote self-learning and simultaneously boost motivation. In this paper, we present our experience ... -
Reproducible SUmmation under HUB Format
Floating point reproducibility is a property claimed by programmers and end users. Half-Unit-Biased (HUB) is a new representation format in which the round to nearest is carried out by truncation, preventing any ... -
Simplified Floating-Point Units for High Dynamic Range Image and Video Systems
Hormigo-Aguilar, Javier; Villalba-Moreno, Julio (2015-06-29)
The upcoming arrival of high dynamic range image and video applications to consumer electronics will force the utilization of floating-point numbers on them. This paper shows that introducing a slight modification on ...