Listar AC - Contribuciones a congresos científicos por título
Mostrando ítems 9-28 de 101
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Adaptive Partition Strategies for Loop Parallelism in Heterogeneous Architectures
(2014-07-30)This paper explores the possibility of efficiently using multicores in conjunction with multiple GPU accelerators under a parallel task programming paradigm. In particular, we address the challenge of extending a ... -
Algoritmos paralelos de memoria compartida que determinan el menor tama˜no de un ´arbol binario al refinar un simplex regular
(2015-10-05)En el ambito de la optimizacion global basada en tecnicas de ramificacion y acotacion, cuando el espacio de busqueda es un n-sımplex regular es habitual utilizar como regla de division la biseccion por el lado mayor, ... -
An Experience of e-assessment in an Introductory Course on Computer Organization
(2013-11-13)This work describes how the CTPracticalsMoodle module can be used for e-assessment in an introductory course on computer organization, where the practical content consists of the design and simulation of a basic CPU ... -
Análisis comparativo del uso de STMs en a códigos de reducción irregulares
(2016-09-20)La memoria transaccional (TM) constituye un paradigma de concurrencia optimista en arquitecturas multinúcleo que puede ser de utilidad en la explotación de paralelismo en aplicaciones irregulares, en las que la información ... -
Analyzing the differences between reads and contigs when performing a taxonomic assignment comparison in metagenomics
(Springer, Cham, 2018-03)Metagenomics is an inherently complex field in which one of the primary goals is to determine the compositional organisms present in an environmental sample. Thereby, diverse tools have been developed that are based on ... -
Aspectos computacionales en la bisección de un n-simplex regular.
(2013-11-05)En el ambito de la optimizacion global basada en tecnicas de ramificacion y acotacion, cuando el espacio de busqueda es un n-simplex regular es habitual utilizar como regla de division la biseccion por el lado mayor. ... -
Barreras especulativas con memoria transaccional
(Sociedad de Arquitectura y Tecnología de Computadores (SARTECO), 2019)La Memoria Transaccional (TM) es una alternativa al modelo de programación basado en locks que pretende simplificar la programación paralela. TM sustituye locks por transacciones para resolver el problema de la exclusión ... -
Boosting Backward Search Throughput for FM-Index Using a Compressed Encoding
(2019-04-11)The rapid development of DNA sequencing technologies has demanded for com- pressed data structures supporting fast pattern matching queries. FM-index is a widely-used compressed data structure that also supports fast ... -
C++ for Heterogeneous Programming: oneAPI (DPC++ and oneTBB)
(2020-11-19)This tutorial provides hands-on experience programming CPUs, GPUs and FPGAs using a unified, standards-based programming model: oneAPI. oneAPI includes a cross-architecture language: Data Parallel C++ (DPC++). DPC++ is an ... -
CodSim 2.0: Un Laboratorio Virtual para la Enseñanza de las Codificaciones de Datos
(SARTECO, 2021-09)Este artículo presenta la herramienta CodSim 2.0, un simulador de codificaciones de datos a nivel físico, dirigido a estudiantes de asignaturas de redes de computadores en grados en ingeniería Informática o Electrónica. El ... -
Computer architecture simulation on the server-side for online evaluation purposes
(2021)Due to the global COVID19 pandemic, in the last few months there has been a dramatic change in the educational context where lecturers around the world has forced to solve academic problems that immediately before this ... -
Control y mejora de la coordinación entre asignaturas de una titulación universitaria
(2015-06-17)Entre las múltiples exigencias que impone el EEES, la mejora de la coordinación entre las asignaturas de una titulación es una de las que más preocupan, y se ha convertido en uno de los temas de debate más vivos en ... -
CUVLE: Variable-Length Encoding on CUDA
(2014-10-14)Data compression is the process of representing information in a compact form, in order to reduce the storage requirements and, hence, communication bandwidth. It has been one of the critical enabling technologies for ... -
Digit recurence division under HUB format
(2016-07-21)Half-Unit-Biased format is based on shifting the representation line of the binary numbers by half Unit in the Last Place. The main feature of this format is that the round to nearest is carried out by a simple truncation, ... -
Diseño del compilador de la máquina virtual inmortal iVM
(Sociedad de Arquitectura y Tecnología de Computadores (SARTECO), 2022-09-21)Conservar la información digital durante mucho tiempo es difı́cil, incluso cuando se utiliza un medio de almacenamiento pasivo duradero, como una pelı́cula fotográfica almacenada en las condiciones adecuadas. En dicho ... -
DNA Sequences Alignment in Multi-GPUs: Energy Payoff on Speculative Executions
(2017-05-30)We present a performance per watt analysis of CUDAlign 4.0, a parallel strategy to obtain the optimal alignment of huge DNA se- quences in multi-GPU platforms using the exact Smith-Waterman method. Speed-up factors and ... -
Efficient Floating-Point Representation for Balanced Codes for FPGA Devices
(2013-10-30)We propose a floating–point representation to deal efficiently with arithmetic operations in codes with a balanced number of additions and multiplications for FPGA devices. The variable shift operation is very slow in ... -
Efficient OpenCL-based concurrent tasks offloading on accelerators
(Procedia Computer Science, 2017)Current heterogeneous platforms with CPUs and accelerators have the ability to launch several independent tasks simultaneously, in order to exploit concurrency among them. These tasks typically consist of data transfer ... -
End-to-end Incremental Learning
(2018-07-06)Although deep learning approaches have stood out in recent years due to their state-of-the-art results, they continue to suffer from (catastrophic forgetting), a dramatic decrease in overall performance when training with ... -
Energy Efficiency of Software Transactional Memory in a Heterogeneous Architecture
(2016-09-07)Hardware vendors make an important effort creating low-power CPUs that keep battery duration and durability above acceptable levels. In order to achieve this goal and provide good performance-energy for a wide variety of ...