• Control y mejora de la coordinación entre asignaturas de una titulación universitaria 

      Ortigosa, Eva M.; Martín Garzón, Ester; Ortigosa, Pilar M.; Casanova, Joaquín O.; Romero, Luis F. (2015-06-17)
      Entre las múltiples exigencias que impone el EEES, la mejora de la coordinación entre las asignaturas de una titulación es una de las que más preocupan, y se ha convertido en uno de los temas de debate más vivos en ...
    • CUVLE: Variable-Length Encoding on CUDA 

      Fuentes-Alventosa, Antonio; Gómez-Luna, Juan; González-Linares, José M.; Guil, Nicolás (2014-10-14)
      Data compression is the process of representing information in a compact form, in order to reduce the storage requirements and, hence, communication bandwidth. It has been one of the critical enabling technologies for ...
    • Digit recurence division under HUB format 

      Villalba-Moreno, Julio (2016-07-21)
      Half-Unit-Biased format is based on shifting the representation line of the binary numbers by half Unit in the Last Place. The main feature of this format is that the round to nearest is carried out by a simple truncation, ...
    • DNA Sequences Alignment in Multi-GPUs: Energy Payoff on Speculative Executions 

      Pérez-Serrano, Jesús; Sandes, Edans; Melo, Alba; Ujaldon-Martinez, Manuel (2017-05-30)
      We present a performance per watt analysis of CUDAlign 4.0, a parallel strategy to obtain the optimal alignment of huge DNA se- quences in multi-GPU platforms using the exact Smith-Waterman method. Speed-up factors and ...
    • Efficient Floating-Point Representation for Balanced Codes for FPGA Devices 

      Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; Corbera, Francisco; Gonzalez, Mario; López-Zapata, Emilio (2013-10-30)
      We propose a floating–point representation to deal efficiently with arithmetic operations in codes with a balanced number of additions and multiplications for FPGA devices. The variable shift operation is very slow in ...
    • Energy Efficiency of Software Transactional Memory in a Heterogeneous Architecture 

      Villegas, Emilio; Villegas, Alejandro; Navarro, Angeles; Asenjo-Plaza, Rafael; Ukidave, Yash; [et al.] (2016-09-07)
      Hardware vendors make an important effort creating low-power CPUs that keep battery duration and durability above acceptable levels. In order to achieve this goal and provide good performance-energy for a wide variety of ...
    • Entropy-based High Performance Computation of Boolean SNP-SNP Interactions Using GPUs 

      Riveros, Carlos; Ujaldon-Martinez, Manuel; Pablo, Moscato (2014-05-02)
      It is being increasingly accepted that traditional statistical Single Nucleotide Polymorphism (SNP) analysis of Genome-Wide Association Studies (GWAS) reveals just a small part of the heritability in complex diseases. ...
    • Evaluación del consumo energético de la memoria transaccional en procesadores heterogéneos 

      Villegas, Emilio; Villegas, Alejandro; Navarro, Angeles; Asenjo-Plaza, Rafael; Plata, Oscar (2016)
      Actualmente existe una enorme cantidad de dispositivos y sistemas, como ordenadores portátiles y teléfonos móviles, que dependen de una batería para su funcionamiento. Como consecuencia, el hardware que incorporan debe ser ...
    • Evaluation of CNN architectures for gait recognition based on optical flow maps 

      Castro, F. M.; Marín-Jiménez, M.J.; Guil, N.; López-Tapia, S.; Pérez de la Blanca, N. (2017)
      This work targets people identification in video based on the way they walk (\ie gait) by using deep learning architectures. We explore the use of convolutional neural networks (CNN) for learning high-level descriptors ...
    • Explotando el nuevo módulo OpenCL de Intel TBB 

      Romero, Jose Carlos; Villegas, Alejandro; Navarro, Angeles; Rodriguez, Andres; Asenjo, Rafael (2018-07-20)
      Este artículo tiene como objetivo contribuir al desarrollo de la programación paralela trabajando en una de las herramientas desarrolladas por Intel: Intel Threading Building Blocks (Intel TBB). Hemos implementado una ...
    • Expressing Heterogeneous Parallelism in C++ with Threading Building Blocks 

      Reinders, James; Voss, Michael J.; Reble, Pablo; Asenjo-Plaza, Rafael (2017-12-18)
      Due to energy constraints, high performance computing platforms are becoming increasingly heterogeneous, achieving greater performance per watt through the use of hardware that is tuned to specific computational kernels ...
    • A first step to accelerating fingerprint matching based on deformable minutiae clustering 

      Romero, Luis F.; Tabik, Siham; Sánchez, Andrés Jesús; Medina Pérez, Miguel Angel; Herrera, Francisco (2018-07-12)
      Fingerprint recognition is one of the most used biometric methods for authentication. The identification of a query fingerprint requires matching its minutiae against every minutiae of all the fingerprints of the database. ...
    • Floating Point Square Root under HUB Format 

      Villalba-Moreno, Julio; Hormigo-Aguilar, Javier (2017-09-26)
      Unit-Biased (HUB) is an emerging format based on shifting the representation line of the binary numbers by half unit in the last place. The HUB format is specially relevant for computers where rounding to nearest is ...
    • Gait recognition and fall detection with inertial sensors 

      Delgado-Escaño, Rubén; Castro, Francisco M.; Marín-Jiménez, Manuel J.; Guil-Mata, Nicolas (2019-11-26)
      In contrast to visual information that is recorded by cameras placed somewhere, inertial information can be obtained from mobile phones that are commonly used in daily life. We present in this talk a general deep learning ...
    • Gait recognition applying Incremental learning 

      Castro, Francisco M.; Marín-Jiménez, Manuel J.; Guil-Mata, Nicolas; Schmid, Cordelia; Alahari, Karteek (2019-11-25)
      when new knowledge needs to be included in a classifier, the model is retrained from scratch using a huge training set that contains all available information of both old and new knowledge. However, in this talk, we present ...
    • Generating order policies by SDP: non-stationary demand and service level constraints 

      Pauls-Worm, Karin G.J.; Hendrix, Eligius Maria Theodorus (2015-07-06)
      Inventory control implies dynamic decision making. Therefore, dynamic programming seems an appropriate approach to look for order policies. For finite horizon planning, the implementation of service level constraints ...
    • GPGPU: Challenges ahead 

      Ujaldon-Martinez, Manuel (2015-11-13)
      Evolución, presente y futuro de la memoria DRAM del computador desde el punto de vista de los procesadores gráficos actuales, y su contribución presente y futura para la aceleración de aplicaciones científicas.
    • GPUs for high performance computing, Deep learning and beyond 

      Ujaldon-Martinez, Manuel (2019-10-24)
      After an impressive evolution within the last decade, Graphics Processing Units (GPUs) constitute nowadays a solid trend to accelerate scientific applications. This talk unveils the GPU architecture from an ...
    • GPUs para HPC: Logros y perspectivas futuras 

      Ujaldon-Martinez, Manuel (2013-10-18)
      Hace una década comenzábamos a mejorar las primeras aplicaciones científicas en GPUs utilizando Cg y OpenGL. Ahora CUDA y OpenCL han tomado el relevo, marcando un ritmo vertiginoso en la aceleración de códigos procedentes ...
    • Hardware support for Local Memory Transactions on GPU Architectures 

      Villegas, Alejandro; Navarro, Ángeles; Asenjo-Plaza, Rafael; Plata, Oscar; Ubal, Rafael; [et al.] (2015-06-26)
      Graphics Processing Units (GPUs) are popular hardware accelerators for data-parallel applications, enabling the execution of thousands of threads in a Single Instruction - Multiple Thread (SIMT) fashion. However, the SIMT ...