• Implementaciones paralelas para un problema de control de inventarios de productos perecederos 

      Gutiérrez Alcoba, Alejandro; Eligius, Hendrix; Inmaculada, García; Ortega, Gloria (2015-10-05)
      En este trabajo se analizan y eval uan dos implementaciones de un algoritmo de optimizaci on para un problema de control de inventarios de productos perecederos. Las implementaciones se han llevado a cabo utilizando ...
    • Improvements in Hardware Transactional Memory for GPU Architectures 

      Villegas, Alejandro; Asenjo-Plaza, Rafael; Navarro, Ángeles; Plata, Oscar (2016-07-20)
      In the multi-core CPU world, transactional memory (TM)has emerged as an alternative to lock-based programming for thread synchronization. Recent research proposes the use of TM in GPU architectures, where a high number of ...
    • Improving Fixed-Point Implementation of QR Decomposition by Rounding-to-Nearest 

      Muñoz, Sergio D.; Hormigo-Aguilar, Javier (2015-06-29)
      QR decomposition is a key operation in many current communication systems. This paper shows how to reduce the area of a fixed-point QR decomposition implementation based on Givens rotations by using a new number ...
    • Improving Transactional Memory Performance for Irregular Applications 

      Pedrero, Manuel; Gutiérrez, Eladio; Romero, Sergio; Plata, Óscar (2015-06-11)
      Transactional memory (TM) offers optimistic concurrency support in modern multicore archi- tectures, helping the programmers to extract parallelism in irregular applications when data dependence information is not available ...
    • Insights into the Fallback Path of Best-Effort Hardware Transactional Memory Systems 

      Quislant, Ricardo; Gutierrez-Carrasco, Eladio Damian; Zapata, Emilio L.; Plata-Gonzalez, Oscar Guillermo (Springer International Publishing, 2016-08-24)
      Current industry proposals for Hardware Transactional Memory (HTM) focus on best-effort solutions (BE-HTM) where hardware limits are imposed on transactions. These designs may show a significant performance degradation ...
    • An Introduction to Intel Threading Building Blocks and its Support for Heterogeneous Programming 

      Asenjo Plaza, Rafael; Cownie, Jim; Fedotov, Aleksei (2018-03-12)
      Due to energy constraints, high performance computing platforms are becoming increasingly heterogeneous, achieving greater performance per watt through the use of hardware that is tuned to specific computational kernels ...
    • Irrevocabilidad Relajada para Memoria Transaccional Hardware 

      Quislant, Ricardo; Gutierrez-Carrasco, Eladio Damian; Zapata, Emilio L.; Plata-Gonzalez, Oscar Guillermo (2016-09-20)
      Los sistemas comerciales que ofrecen memoria transaccional (TM) implementan un sistema hardware best-effort (BE-HTM) con limitaciones. Es necesario programar un fallback software basado en cerrojos para asegurar el progreso ...
    • Localizando partículas en un fluido a partir de holografías y computación de altas prestaciones 

      Ortega, Gloria; Lobera, Julia; García, Inmaculada; Arroyo, Maria del Pilar; Garzon, Ester M. (2014-09-24)
      La tomografía se ha introducido recientemente en la velocimetría de fluidos para proporcionar información en tres dimensiones de la localización de partículas en el seno de fluidos. En concreto, algunos trabajos previos ...
    • Low-textured regions detection for improving stereoscopy algorithms 

      Ibarra-Delgado, Salvador; Ramos Cózar, Julián; González-Linares, José M.; Gómez Luna, Juan; Guil, Nicolás (2014-07-29)
      The main goal of stereoscopy algorithms is the calculation of the disparity map between two frames corresponding to the same scene, and captured simultaneously by two different cameras. The different position (disparity) ...
    • Memoria Transaccional Hardware en Memoria Local de GPU 

      Villegas, Alejandro; Navarro, Ángeles; Asenjo-Plaza, Rafael; Plata, Oscar (2015-09-25)
      Los aceleradores gráficos (GPUs) se han convertido en procesadores de prop ́osito general muy populares para el cómputo de aplicaciones que presen- tan un gran paralelismo de datos. Su modelo de ejecución SIMT (Single ...
    • Memoria Transaccional Software en Procesadores CPU+GPU Heterogéneos 

      Navarro, Angeles; Asenjo-Plaza, Rafael; Plata-Gonzalez, Oscar Guillermo; Villegas, Alejandro (2018-09-19)
      En los procesadores multi-núcleo, la memoria transaccional (TM) ha aparecido como una alternativa prometedora a las técnicas basadas en cerrojos para garantizar exclusión mutua y está siendo incluida como parte de procesadores ...
    • Modelling vessel fleet composition for maintenance operations at offshore wind farms 

      Gutiérrez-Alcoba, Alejandro; Garcia, Inmaculada; Ortega López, Gloria; Hendrix, Eligius Maria Theodorus (2018-12-20)
      Chartering a vessel fleet to support maintenance operations at offshore wind farms (OWF's) constitutes one of the major costs of maintaining this type of installations. Literature describes deterministic optimization models ...
    • Normalizing or not normalizing? An open question for floating-point arithmetic in embedded systems 

      González-Navarro, Sonia; Hormigo-Aguilar, Javier (IEEE, 2017-07-24)
      Emerging embedded applications lack of a specific standard when they require floating-point arithmetic. In this situation they use the IEEE-754 standard or ad hoc variations of it. However, this standard was not designed ...
    • On computational procedures for Value Iteration in inventory control 

      Kortenhorst, Cleo; Ortega, Gloria L; Hendrix, Eligius Maria Theodorus (2019-09-11)
      Dynamic programming (DP) is often seen in inventory control to lead to optimal ordering policies. When considering stationary demand, Value Iteration (VI) may be used to derive the best policy. In this paper, our focus is ...
    • On the parallelization of a three-parametric log-logistic estimation algorithm 

      Asenjo-Plaza, Rafael; Rodríguez, Andrés; Navarro, Ángeles; Fernández-Madrigal, Juan Antonio; Cruz-Martin, Ana Maria (2014-09-25)
      Networked telerobots transmit data from its sensors to the remote controller. To provide guarantees on the time requirements of these systems it is mandatory to keep the transmission time delays below a given threshold, ...
    • Optimizing DSP Circuits by a New Family of Arithmetic Operators 

      Hormigo-Aguilar, Javier; Villalba-Moreno, Julio (2014-11-19)
      A new family of arithmetic operators to optimize the implementation of circuits for digital signal processing is presented. Thanks to use of a new technique which reduces the quantification errors, the proposed operators ...
    • Pairwise and incremental multi-stage alignment of metagenomes: A new proposal 

      Pérez-Wohlfeil, Esteban; Torreno, Oscar; Trelles-Salazar, Oswaldo Rogelio (Springer, 2017)
      Traditional comparisons between metagenomes are often performed using reference databases as intermediary templates from which to obtain distance metrics. However, in order to fully exploit the potential of the information ...
    • Paralelismo de datos en la obtención de Tablas de Control de Tráfico con información de llegada 

      Herrera, Juan Francisco R.; Casado, Leocadio G.; Haijema, Rene; Hendrix, Eligius Maria Theodorus (2014-09-24)
      Los semáforos se pueden controlar de forma dinámica a través de varias reglas que dictaminan el color del semáforo segun el número de vehículos a la espera. Estas reglas o acciones se recogen en lo que se conoce como ...
    • Path planning for socially-aware humanoid robots 

      Constantinescu, Denisa-Andreea; Rohra, Aakash; Padir, Taskin; Kaeli, David; Rohra (2019-04-11)
      Designing efficient autonomous navigation systems for mobile robots involves consideration of the robotís environment while arriving at a systems architecture that trades off multiple constraints. We have architected a ...
    • Patrón pipeline aplicado a arquitecturas heterogéneas big.LITTLE 

      Vilches, Antonio; Rodriguez, Andres; Navarro, Ángeles; Corbera, Francisco; Asenjo-Plaza, Rafael (2015-09-25)
      En este trabajo, proponemos una solución para permitir la ejecución de aplicaciones de tipo streaming, que constan de una serie de etapas, sobre arquitecturas heterogéneas con un multicore y una GPU integrada. Para ello, ...