• Digit recurence division under HUB format 

      Villalba-Moreno, Julio (2016-07-21)
      Half-Unit-Biased format is based on shifting the representation line of the binary numbers by half Unit in the Last Place. The main feature of this format is that the round to nearest is carried out by a simple truncation, ...
    • Efficient Floating-Point Representation for Balanced Codes for FPGA Devices 

      Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; Corbera, Francisco; Gonzalez, Mario; López-Zapata, Emilio (2013-10-30)
      We propose a floating–point representation to deal efficiently with arithmetic operations in codes with a balanced number of additions and multiplications for FPGA devices. The variable shift operation is very slow in ...
    • Optimizing DSP Circuits by a New Family of Arithmetic Operators 

      Hormigo-Aguilar, Javier; Villalba-Moreno, Julio (2014-11-19)
      A new family of arithmetic operators to optimize the implementation of circuits for digital signal processing is presented. Thanks to use of a new technique which reduces the quantification errors, the proposed operators ...
    • Reproducible SUmmation under HUB Format 

      Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; Jaime Rodriguez, Francisco Jose
      Floating point reproducibility is a property claimed by programmers and end users. Half-Unit-Biased (HUB) is a new representation format in which the round to nearest is carried out by truncation, preventing any ...