ListarAC - Contribuciones a congresos científicos por tema "Computer arithmetic"
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Efficient Floating-Point Representation for Balanced Codes for FPGA Devices
(2013-10-30)We propose a floating–point representation to deal efficiently with arithmetic operations in codes with a balanced number of additions and multiplications for FPGA devices. The variable shift operation is very slow in ... -
Reproducible SUmmation under HUB Format
Floating point reproducibility is a property claimed by programmers and end users. Half-Unit-Biased (HUB) is a new representation format in which the round to nearest is carried out by truncation, preventing any ...