The upcoming arrival of high dynamic range image
and video applications to consumer electronics will force the
utilization of floating-point numbers on them. This paper shows
that introducing a slight modification on classical floating-point
number systems, the implementation of those circuits can be
highly improved. For a 16-bit numbers, by using the proposed
format, the area and power consumption of a floating-point
adder is reduced up to 70% whereas those parameters are
maintained for the case of a multiplier.
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