Floating Point HUB Adder for RISC-V Sargantana Processor

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dc.contributor.authorBandera-Burgueño, Gerardo
dc.contributor.authorSalamero, Javier
dc.contributor.authorMoreto, Miquel
dc.contributor.authorVillalba-Moreno, Julio
dc.date.accessioned2024-02-08T16:16:36Z
dc.date.available2024-02-08T16:16:36Z
dc.date.issued2023
dc.departamentoArquitectura de Computadores
dc.description.abstractHUB format is an emerging technique to improve the hardware and time requirement when round to nearest is needed. On the other hand, RISC-V is a open source ISA that an important number of companies are using in their designs currently. In this paper we present a tailored floating point HUB adder that has been implemented in the Sargantana RISC-V processores_ES
dc.identifier.citationG Bandera, J Salamero, M Moreto, J Villalba. Floating Point HUB Adder for RISC-V Sargantana Processor. RISC-V Summit Europe, Barcelona, 5-9th June 2023es_ES
dc.identifier.doi10.48550/arXiv.2401.09464
dc.identifier.urihttps://hdl.handle.net/10630/30192
dc.language.isoenges_ES
dc.publisherCornell Universityes_ES
dc.rights.accessRightsopen accesses_ES
dc.subjectHardwarees_ES
dc.subject.otherHUB formates_ES
dc.subject.otherRISC-Ves_ES
dc.subject.otherISAes_ES
dc.subject.otherFPUes_ES
dc.titleFloating Point HUB Adder for RISC-V Sargantana Processores_ES
dc.typejournal articlees_ES
dc.type.hasVersionVoRes_ES
dspace.entity.typePublication
relation.isAuthorOfPublication63245157-a2a2-4980-9f45-a83ac108e7ef
relation.isAuthorOfPublicatione84e469e-87d4-4dcc-a0bf-d73e8abb14f2
relation.isAuthorOfPublication.latestForDiscovery63245157-a2a2-4980-9f45-a83ac108e7ef

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