Floating Point HUB Adder for RISC-V Sargantana Processor
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Cornell University
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Abstract
HUB format is an emerging technique to improve the hardware and time requirement when round to nearest is
needed. On the other hand, RISC-V is a open source ISA that an important number of companies are using in
their designs currently. In this paper we present a tailored floating point HUB adder that has been implemented
in the Sargantana RISC-V processor
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G Bandera, J Salamero, M Moreto, J Villalba. Floating Point HUB Adder for RISC-V Sargantana Processor. RISC-V Summit Europe, Barcelona, 5-9th June 2023