Arquitectura HW para decodificador Two-Step SOVA con recorridos hacia atrás sistólicos

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dc.centroE.T.S.I. Telecomunicaciónes_ES
dc.contributor.authorMartín-Vega, Francisco-Javier
dc.contributor.authorLópez-Martínez, Francisco Javier
dc.contributor.authorEntrambasaguas-Muñoz, José Tomás
dc.date.accessioned2022-02-06T21:31:50Z
dc.date.available2022-02-06T21:31:50Z
dc.date.issued2012-09-12
dc.departamentoIngeniería de Comunicaciones
dc.description.abstractIn this paper, a novel SOVA (Soft-Output Viterbi algorithm) decoder using systolic arrays to carry out the trace-back method is presented. Systolic arrays are associated with high data rates and small resource requirements, so they are especially attractive for efficient hardware implementations. The proposed architecture offers excellent performance in terms of throughput and has been used to implement a turbo decoder compliant to the 3GPP-LTE specification.es_ES
dc.description.sponsorshipUniversidad de Málaga. Campus de Excelencia Internacional Andalucía Tech.es_ES
dc.identifier.urihttps://hdl.handle.net/10630/23749
dc.language.isospaes_ES
dc.relation.eventdate12/09/2012es_ES
dc.relation.eventplaceElche (Spain)es_ES
dc.relation.eventtitleXXVII Simposium Nacional de la Unión Científica Internacional de Radio (URSI)es_ES
dc.rights.accessRightsopen accesses_ES
dc.subjectSistemas informáticoses_ES
dc.subject.otherFPGAes_ES
dc.subject.othercodificación de canales_ES
dc.subject.otherturbo decodificaciónes_ES
dc.subject.othersoft-output Viterbi algorithmes_ES
dc.subject.otherLTEes_ES
dc.titleArquitectura HW para decodificador Two-Step SOVA con recorridos hacia atrás sistólicoses_ES
dc.typeconference outputes_ES
dspace.entity.typePublication
relation.isAuthorOfPublicationf4f194c9-ddcb-4b50-abf2-78d6792a5f8f
relation.isAuthorOfPublication.latestForDiscoveryf4f194c9-ddcb-4b50-abf2-78d6792a5f8f

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