Arquitectura HW para decodificador Two-Step SOVA con recorridos hacia atrás sistólicos

Abstract

In this paper, a novel SOVA (Soft-Output Viterbi algorithm) decoder using systolic arrays to carry out the trace-back method is presented. Systolic arrays are associated with high data rates and small resource requirements, so they are especially attractive for efficient hardware implementations. The proposed architecture offers excellent performance in terms of throughput and has been used to implement a turbo decoder compliant to the 3GPP-LTE specification.