Configurable Ultra-High-Throughput QRD FPGA Accelerators for small matrices.

Abstract

QR decomposition is an essential operation in matrix algebra that is applicable in many fields, such as signal processing, automatic control, communications, and physics simulations. The QRD computation is the system’s bottleneck in many of these applications. This paper presents a configurable ultra-high-throughput accelerator for FPGAs designed using High-Level Synthesis language. The accelerator is arranged as a 2D-systolic array of Givens rotators based on the CORDIC algorithm. Its dimension can be configured at compilation time to fit the matrix size. Similarly, the degree of parallelism in the rotators can be configured, such as the computation throughput goes from one n × n matrix every 2n clock cycles up to one matrix every clock cycle.