Aceleración HW con FPGA de la codificación de canal mediante el interfaz PCIe y DMA.

Abstract

Hardware acceleration has gained renewed interest recently due to its great potential to solve the computational burdens associated with SW based implementation of real time communication systems. This approach considers SW based implementation of most of the communication functions due to its fast development cycles and great flexibility compared to HW development. However, those functions that are computationally demanding are implemented in HW to greatly reduce the computational time. Due to its iterative nature, channel encoding and decoding is related to high computational costs. This motivated us to develop a solution to this problem by offloading the encoding function to an FPGA. To minimize communication time between the computer and the FPGA, the PCIe interface is used, which achieves high transfer speeds. The results show the encoding of the message both in the computer and in the FPGA, along with their corresponding validation and performance metrics.