• A first step to accelerating fingerprint matching based on deformable minutiae clustering 

      Romero, Luis F.; Tabik, Siham; Sánchez, Andrés Jesús; Medina Pérez, Miguel Angel; Herrera, Francisco (2018-07-12)
      Fingerprint recognition is one of the most used biometric methods for authentication. The identification of a query fingerprint requires matching its minutiae against every minutiae of all the fingerprints of the database. ...
    • Floating Point Square Root under HUB Format 

      Villalba-Moreno, Julio; Hormigo-Aguilar, Javier (2017-09-26)
      Unit-Biased (HUB) is an emerging format based on shifting the representation line of the binary numbers by half unit in the last place. The HUB format is specially relevant for computers where rounding to nearest is ...
    • Gait recognition and fall detection with inertial sensors 

      Delgado-Escaño, Rubén; Castro, Francisco M.; Marín-Jiménez, Manuel J.; Guil-Mata, Nicolas (2019-11-26)
      In contrast to visual information that is recorded by cameras placed somewhere, inertial information can be obtained from mobile phones that are commonly used in daily life. We present in this talk a general deep learning ...
    • Gait recognition applying Incremental learning 

      Castro, Francisco M.; Marín-Jiménez, Manuel J.; Guil-Mata, Nicolas; Schmid, Cordelia; Alahari, Karteek (2019-11-25)
      when new knowledge needs to be included in a classifier, the model is retrained from scratch using a huge training set that contains all available information of both old and new knowledge. However, in this talk, we present ...
    • Generating order policies by SDP: non-stationary demand and service level constraints 

      Pauls-Worm, Karin G.J.; Hendrix, Eligius Maria Theodorus (2015-07-06)
      Inventory control implies dynamic decision making. Therefore, dynamic programming seems an appropriate approach to look for order policies. For finite horizon planning, the implementation of service level constraints ...
    • GPGPU: Challenges ahead 

      Ujaldon-Martinez, Manuel (2015-11-13)
      Evolución, presente y futuro de la memoria DRAM del computador desde el punto de vista de los procesadores gráficos actuales, y su contribución presente y futura para la aceleración de aplicaciones científicas.
    • GPUs for high performance computing, Deep learning and beyond 

      Ujaldon-Martinez, Manuel (2019-10-24)
      After an impressive evolution within the last decade, Graphics Processing Units (GPUs) constitute nowadays a solid trend to accelerate scientific applications. This talk unveils the GPU architecture from an ...
    • GPUs para HPC: Logros y perspectivas futuras 

      Ujaldon-Martinez, Manuel (2013-10-18)
      Hace una década comenzábamos a mejorar las primeras aplicaciones científicas en GPUs utilizando Cg y OpenGL. Ahora CUDA y OpenCL han tomado el relevo, marcando un ritmo vertiginoso en la aceleración de códigos procedentes ...
    • Hardware support for Local Memory Transactions on GPU Architectures 

      Villegas, Alejandro; Navarro, Ángeles; Asenjo-Plaza, Rafael; Plata, Oscar; Ubal, Rafael; [et al.] (2015-06-26)
      Graphics Processing Units (GPUs) are popular hardware accelerators for data-parallel applications, enabling the execution of thousands of threads in a Single Instruction - Multiple Thread (SIMT) fashion. However, the SIMT ...
    • Hardware support for scratchpad memory transactions on GPU architectures 

      Villegas, Alejandro; Asenjo-Plaza, Rafael; Navarro, Angeles; Plata, Oscar; Ubal, Rafael; [et al.] (Springer, 2017-08-29)
      Graphics Processing Units (GPUs) have become the accelerator of choice for data-parallel applications, enabling the execution of thousands of threads in a Single Instruction - Multiple Thread (SIMT) fashion. Using OpenCL ...
    • Heuristics for Longest Edge Selection in Simplicial Branch and Bound 

      Herrera, Juan F.R.; Casado, Leocadio G.; Hendrix, Eligius Maria Theodorus; García, Inmaculada (2015-07-06)
      Simplicial partitions are suitable to divide a bounded area in branch and bound. In the iterative re nement process, a popular strategy is to divide simplices by their longest edge, thus avoiding needle-shaped simplices. ...
    • HPC Accelerators with 3D Memory 

      Ujaldon-Martinez, Manuel (2016-09-13)
      After a decade evolving in the High Performance Computing arena, GPU-equipped supercomputers have con- quered the top500 and green500 lists, providing us unprecedented levels of computational power and memory bandwidth. ...
    • Implementaciones paralelas para un problema de control de inventarios de productos perecederos 

      Gutiérrez Alcoba, Alejandro; Eligius, Hendrix; Inmaculada, García; Ortega, Gloria (2015-10-05)
      En este trabajo se analizan y eval uan dos implementaciones de un algoritmo de optimizaci on para un problema de control de inventarios de productos perecederos. Las implementaciones se han llevado a cabo utilizando ...
    • Improvements in Hardware Transactional Memory for GPU Architectures 

      Villegas, Alejandro; Asenjo-Plaza, Rafael; Navarro, Ángeles; Plata, Oscar (2016-07-20)
      In the multi-core CPU world, transactional memory (TM)has emerged as an alternative to lock-based programming for thread synchronization. Recent research proposes the use of TM in GPU architectures, where a high number of ...
    • Improving Fixed-Point Implementation of QR Decomposition by Rounding-to-Nearest 

      Muñoz, Sergio D.; Hormigo-Aguilar, Javier (2015-06-29)
      QR decomposition is a key operation in many current communication systems. This paper shows how to reduce the area of a fixed-point QR decomposition implementation based on Givens rotations by using a new number ...
    • Improving Transactional Memory Performance for Irregular Applications 

      Pedrero, Manuel; Gutiérrez, Eladio; Romero, Sergio; Plata, Óscar (2015-06-11)
      Transactional memory (TM) offers optimistic concurrency support in modern multicore archi- tectures, helping the programmers to extract parallelism in irregular applications when data dependence information is not available ...
    • Insights into the Fallback Path of Best-Effort Hardware Transactional Memory Systems 

      Quislant, Ricardo; Gutierrez-Carrasco, Eladio Damian; Zapata, Emilio L.; Plata-Gonzalez, Oscar Guillermo (Springer International Publishing, 2016-08-24)
      Current industry proposals for Hardware Transactional Memory (HTM) focus on best-effort solutions (BE-HTM) where hardware limits are imposed on transactions. These designs may show a significant performance degradation ...
    • An Introduction to Intel Threading Building Blocks and its Support for Heterogeneous Programming 

      Asenjo Plaza, Rafael; Cownie, Jim; Fedotov, Aleksei (2018-03-12)
      Due to energy constraints, high performance computing platforms are becoming increasingly heterogeneous, achieving greater performance per watt through the use of hardware that is tuned to specific computational kernels ...
    • Irrevocabilidad Relajada para Memoria Transaccional Hardware 

      Quislant, Ricardo; Gutierrez-Carrasco, Eladio Damian; Zapata, Emilio L.; Plata-Gonzalez, Oscar Guillermo (2016-09-20)
      Los sistemas comerciales que ofrecen memoria transaccional (TM) implementan un sistema hardware best-effort (BE-HTM) con limitaciones. Es necesario programar un fallback software basado en cerrojos para asegurar el progreso ...
    • Localizando partículas en un fluido a partir de holografías y computación de altas prestaciones 

      Ortega, Gloria; Lobera, Julia; García, Inmaculada; Arroyo, Maria del Pilar; Garzon, Ester M. (2014-09-24)
      La tomografía se ha introducido recientemente en la velocimetría de fluidos para proporcionar información en tres dimensiones de la localización de partículas en el seno de fluidos. En concreto, algunos trabajos previos ...